1. Field of the Invention
The invention relates to operation of semiconductor device and a semiconductor apparatus, and more particularly to a method for programming a multi-level cell and a memory apparatus using the programming method.
2. Description of Related Art
With the rising demand for memory capacity of electronic products, the memory in which each cell has two storage sites and is thus capable of storing two or more bits has gradually become the mainstream, but such memory suffers from interference between the two storage sites in operation, which is commonly called the 2nd-bit effect.
FIG. 1 illustrates a conventional non-volatile cell having two storage sites and possible threshold voltages (Vt) distributions of each storage site. The cell 10 includes a substrate 100, a gate 110, a charge trapping layer 120 between the substrate 100 and the gate 110, two doping regions 130 in the substrate 100 beside the gate 110. The first/second storage site 122/124 is located in the charge trapping layer 120 near the first/second doping region 130.
Such memory cell usually adopts reverse read. Taking the first storage site 122 as an example, during its reading a depletion region 140 is formed below the second storage site 124 to prevent influence by the charges in the same. However, when there are numerous charges in the second storage site 124 with a distribution range exceeding the border of the depletion region 140, the reading of the first storage site 122 is affected, which is one of the causes of the 2nd-bit effect.
Referring again to FIG. 1, in a multi-level operation mode, when each of the first storage site 122 and the second storage site 124 has a variation of 4 Vt levels, each cell can store 4 bits (4×4=16=24). The lowest first level corresponds to the state of not storing any charge, whose Vt distribution is wider due to the influence of the fabrication process while the central value of the Vt distribution increases with the ascending storage amount of charges in the other storage site (i.e., the rise in the Vt level). That is, the central values of the distributions D1, D2, D3 and D4 of the 1st Vt level of the second storage site 124 (or the first storage site 122) when the first storage site 122 (or the second storage site 124) is at the 1st, 2nd, 3rd and 4th levels respectively are in the order of D4>D3>D2>D1. As for the 2nd to 4th levels corresponding to the states of storing charges, their Vt distributions are narrower because of the advancement in the programming technology and are not influenced by the 2nd-bit effect.
Since the Vt distribution width of the 1st level varies with the 2nd-bit effect, a Vt margin has to be reserved when setting the 2nd level to prevent mis-reading resulting from an overly small reading window between the first and second levels. However, the Vt margin can not be set as overly large. Therefore, the reading window between the first and second levels is still insufficient, which is adverse to the miniaturization of the memory cell.